1. Technical Field
The present invention pertains to synchronization of signals. In particular, the present invention pertains to a delay locked loop circuit that produces a signal synchronized to an externally supplied signal and compensates for frequency drift in that external signal.
2. Discussion of the Related Art
Generally, a delay locked loop circuit (DLL) reduces or compensates for a skew between a clock signal and data or between an external clock and an internal clock. For example, the delay locked loop may be used to synchronize an internal clock of a synchronous memory to an external clock without incurring any error. Typically, a timing delay occurs when a clock provided externally is used within the apparatus. The delay locked loop controls the timing delay to synchronize the internal clock to the external clock.
A conventional DLL is illustrated in FIG. 1. Specifically, DLL 10 includes an input receiver 15, a variable delay line 20, an off-chip driver 30, a phase detector 40, a counter 50 and a feedback circuit 60. The input receiver receives an external clock signal (CLK) and produces an internal clock signal (CLK2DLL) for transference to variable delay line 20 and phase detector 40. The internal clock signal includes an initial delay (T1) corresponding to the delay or amount of processing time utilized by the input receiver. The variable delay line delays the internal clock signal by an amount (T2) corresponding to a phase difference between the internal clock (CLK2DLL) and feedback (FBCLK) signals as described below. The resulting signal from the variable delay line (DCLK) is transferred to off-chip driver 30 and to feedback circuit 60. The driver further delays the signal by a delay or amount of processing time (δr) utilized by the driver and provides a clock signal (DQS) synchronized with the external clock signal (CLK) to other circuits.
The feedback circuit receives the signal (DCLK) from the variable delay line and includes delay elements producing a delay (Tf) corresponding to the delays of the input receiver (T1) and the driver (δr). Thus, the resulting feedback signal (FBCLK) produced by the feedback circuit simulates the delays (Tf=T1+δr) encountered by the external clock signal (CLK). The feedback signal (FBCLK) and internal clock signal (CLK2DLL) are received by phase detector 40 that determines the phase difference or skew between these signals, thereby indicating the phase difference between the internal and external clock signals (CLK and DQS).
The phase detector controls counter 50 to indicate the phase difference between the internal clock and feedback signals. The phase detector generally increments or decrements the counter to enable the count to indicate the phase difference. The count basically represents the phase difference in terms of a quantity of delay elements or units of the variable delay line. The counter controls the delay provided by variable delay line 20 to compensate for the phase difference between the signals (CLK2DLL and FBCLK) and enable the resulting signal (DQS) to become synchronized with the external clock signal (CLK). In other words, the DLL determines the delay (T2) of the variable delay line to align the resulting signal from the driver (DQS) with the external clock signal (CLK). The delay of the delay line (T2) may be expressed as follows:T2=K*Tcycle−Tf, where K*Tcycle is an integer multiple of the external clock signal period. The various DLL signals and corresponding skews are illustrated in the timing diagrams of FIG. 1.
The DLL typically operates over a clock frequency range to lock onto a particular clock or operational frequency. By way of example only, the DLL may operate in the frequency range of 80 MHz–600 MHz (or clock cycles (Tcycle) in the range of approximately 1.6 to 12.5 nanoseconds). In this case, counter 50 includes a value between zero and 2P−1, where P represents the quantity of bits utilized for the count. Once the DLL is locked onto or reset for a clock frequency, systems may change the operating or clock frequency for power saving or other purposes without resetting the DLL. The DLL operates under the lock condition parameters until the counter reaches a minimum or maximum value. At this point, the delay within the DLL is likely to become insufficient to align the clock signals (CLK and DQS), where the resulting clock signal (DQS) does not become synchronized with the external signal (CLK).
Basically, two situations may arise in response to the frequency change. One situation is referred to as “overflow” and the other situation is referred to as “underflow”. Overflow occurs when a maximum delay of the DLL is reached (e.g., the counter reaches a maximum count value or a value of 2P−1). A further decrease in the clock frequency (or increase in the clock period) will require a delay which the DLL cannot accommodate (e.g., the delay required will be beyond the maximum delay of the DLL). The overflow condition is illustrated, by way of example only, in FIG. 2A. The first time line graphically illustrates the external clock signal (CLK) with the DLL locked to a clock period or Tcycle of five nanoseconds. The resulting signal (DQS) is delayed by a feedback circuit delay (Tf) of six nanoseconds, thereby providing a variable delay line delay (T2) of four nanoseconds (e.g., T2=K*Tcycle−Tf as described above, where the lock occurs at K=2) to align the external clock and resulting signals (CLK and DQS). The second time line graphically illustrates the external clock signal (CLK) with the DLL locked to a clock period or Tcycle of ten nanoseconds. The resulting signal (DQS) is delayed by the feedback circuit delay (Tf) of six nanoseconds, thereby providing a variable delay line delay (T2) of four nanoseconds (e.g., T2=K*Tcycle−Tf as described above, where the lock occurs at K=1) to align the external clock and resulting signals (CLK and DQS). The third time line graphically illustrates the change in period (Tcycle) of the external clock signal (CLK) from five nanoseconds to ten nanoseconds with the DLL locked to a clock period or Tcycle of five nanoseconds and K=2 (e.g., as in the first time line). The resulting signal (DQS) is delayed by the feedback circuit delay (Tf) of six nanoseconds, thereby providing a variable delay line delay (T2) of fourteen nanoseconds (e.g., T2=K*Tcycle−Tf as described above, where the lock occurs at K=2) to align the external clock and resulting signals (CLK and DQS). Since the maximum delay of the variable delay line is on the order of a maximum Tcycle (or twelve nanoseconds for 80 MHz as described above), the delay needed to synchronize the external clock and resulting signals (CLK and DQS) is beyond the capability of the DLL.
The second situation or underflow occurs when the delay (T2) needed for the DLL to lock is zero (e.g., the counter reaches a count value of zero). A further increase in clock frequency (or decrease in clock period) will require a negative delay which is not possible. The underflow condition is illustrated, by way of example only, in FIG. 2B. The first time line graphically illustrates the external clock signal (CLK) with the DLL locked to a clock period or Tcycle of five nanoseconds. The resulting signal (DQS) is delayed by a feedback circuit delay (Tf) of six nanoseconds, thereby providing a variable delay line delay (T2) of four nanoseconds (e.g., T2=K*Tcycle−Tf as described above, where the lock occurs at K=2) to align the external clock and resulting signals (CLK and DQS). The second time line graphically illustrates the external clock signal (CLK) with the DLL locked to a clock period or Tcycle of ten nanoseconds. The resulting signal (DQS) is delayed by the feedback circuit delay (Tf) of six nanoseconds, thereby providing a variable delay line delay (T2) of four nanoseconds (e.g., T2=K*Tcycle−Tf as described above, where the lock occurs at K=1) to align the external clock and resulting signals (CLK and DQS). The third time line graphically illustrates the change in period (Tcycle) of the external clock signal (CLK) from ten nanoseconds to five nanoseconds with the DLL locked to a clock period or Tcycle of ten nanoseconds and K=1 (e.g., as in the second time line). The resulting signal (DQS) is delayed by the feedback circuit delay (Tf) of six nanoseconds, thereby providing a negative variable delay line delay (T2) of one nanosecond (e.g., T2=K*Tcycle−Tf as described above, where the lock occurs at K=1) to align the external clock and resulting signals (CLK and DQS). Since the minimum delay of the variable delay line is zero or no delay, the negative delay needed to synchronize the external clock and resulting signals (CLK and DQS) is beyond the capability of the DLL.
A proposed solution is to utilize additional delay lines. For example, two lines may be used for the external and feedback clock signals (CLK and FBCLK), while a third delay line may be utilized as a reference for the DLL. In response to an overflow or underflow condition, the DLL is automatically reset to lock onto a new clock frequency. The reset may be applied with or without the additional delay lines to accommodate the underflow or overflow condition. Another proposed solution is to increase the amount of the delay in the delay line.
However, the proposed solutions suffer from several disadvantages. In particular, the use of additional delay or delay lines reduces the area on integrated circuits or chips, and increases jitter, power or current consumption and complexity of the circuit. Further, the use of a DLL reset produces a locking period that prevents use of the DLL during that period (e.g., the output of the DLL may not be used for a period on the order of a few hundred clock cycles).
The present invention accommodates the overflow and underflow conditions with the proper amount of delay (e.g., on the order of the maximum clock period or Tcycle) in the DLL. When the DLL reaches an overflow or underflow condition, the DLL is still presumably locked since the frequency drift is slow relative to the update rate of the DLL, where the latency of the locked loop is represented by K. In the case of an overflow condition, the next locking position is typically within the preceding clock period (e.g., K−1), while the next locking position for an underflow condition is typically within the succeeding clock period (e.g., K+1). The present invention decrements the DLL counter in response to an overflow condition by the number of coarse delay elements within a clock period to enable locking within the preceding clock period. Similarly, the present invention increments the DLL counter in response to an underflow condition by the number of coarse delay elements within a clock period to enable locking within the succeeding clock period.